TMP: Master Plan

Fri, 19 Jun 2009 18:07:54 +0000

I spent a lot of time debating which ISA to base this on. MIPS has the advantages of being easy to explain, being a good example of RISC, and I’ve implemented large sections of it before for class. However, that last bit makes me wary, because it means that more students in a similar situation will need to implement a MIPS-like processor. I don’t want to just give away final projects here, so anything resembling MIPS enough to allow people to literally copy large sections of the code I release is undesirable. The other option that comes to mind is something based on ARM’s ISA. ARM is well-established and is a very common platform for embedded systems, but at the same time. So I’ll use a handful of the really interesting features available in ARM’s ISA, such as conditional execution of instructions. Finally, it’s never fun to blindly implement someone else’s ISA, it’s much more interesting to create your own design, so ultimately I will draw on both MIPS and ARM, as well as my own intuition, and create something that incorporates what I think are important features from both, while at the same time lending itself well to explanation of key features.

The Master Plan, then, loosely resembles the following, with many stages happening in parallel:

Design Instruction Set Architecture (ISA)
- Should be Load-Store and adhere to basic RISC principles.
- Should make it easy to explain and demonstrate basic design principles, while allowing for powerful features and extensibility.
Create a Simulator
- Written in C
- Will require an additional, simple assembler to convert instruction mnemonics to a binary execution image
- Initially command line based (or ncurses frontend), with the possibility of adding a GUI if it seems worthwhile
Design ALU
- This part, and everything leading up to the actual processor implementation connecting everything together, can happen in parallel with simulator programming
Create Register File
Miscellaneous Processor Structures
- Memory interface (initially, an ideal memory, so this will just decode/translate requests)
- Forwarding/Hazard Detection and Handling
- Pipeline Registers
Assemble the Microprocessor
- This includes pipelining
- Support for multiply and divide instructions
  - Requires significant pipeline extensions and an additional parallel processing unit
- Support for interrupts
  - This is necessary for implementing any reasonable, albeit basic, operating system
  - Also necessary for I/O, which is quite reasonable for anyone using integrated FPGA development boards (which often have a lot of I/O and the necessary support circuitry already implemented)
  - Not covered/explained often in microprocessor courses, yet integral to the functionality of all modern computers (interrupts are used to make system calls in both Windows and Linux).
- A basic OS
  - Flat memory model, without memory protection (dangerous, but simple)
  - Cooperative Multithreading (because it’s easy to implement)
  - Implements basic system calls to provide common sets of functionality for user programs
With this list of central goals complete, a few additional features seem quite reasonable and would serve to be important in understanding the functionality of a much more advanced processor. Therefore, these are secondary targets, to be completed once the basic design is done:
- Instruction and Data Cache
- Branch Predictor
I’ve even got some genuinely crazy ideas, but I’ll keep them to myself for now (most fall into the realm of “not existent on 99% of available commercial microprocessors/microcontrollers”). If this can be established as a platform on which I can test less mainstream concepts and designs, then this will be a success for me.

All that said, I may have missed a few features that won’t be apparent until the time comes, but I think this is a good starting point. Next time, the ISA will be unveiled (hopefully a week), or at least the first revision of it. Design flaws will always become apparent through actually working with it (something a lot of software library designers haven’t realized, but I digress), and so things will be amended as time goes on.

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The Microprocessor Project: Overview

Fri, 12 Jun 2009 19:45:02 +0000

This summer, I need something to do. I’ve got a few ideas, but in particular, one desire I’ve had since I was a young teenager was to design my own computer, which I’ve now learned enough to understand means “to design my own microprocessor.” Software for it can come later, if I still like the idea after designing the hardware (or, if I’m really clever, I can try to port Linux to it, and not have to write my own software at all). However, I see now that the reason I didn’t do this sooner, and my new reason for doing this project, is that there are virtually no in-depth, beginner-level resources available on the Internet (if anyone wants to try to look at OpenSPARC and without any understanding of what it’s based on, deduce how to build a basic microprocessor, please, be my guest). To that end, today I begin my next big project: designing, simulating, testing, and maybe putting on an FPGA a real, functional, 32-bit microprocessor. Then, explaining it in detail, putting my results on the Internet, and releasing it under the GNU GPL, so that there exists a simple platform for people to play around with microprocessors, extending it with additional features or modules as they see fit. I don’t intend to create something remotely commercially viable, because I will, initialy, purposely not include features found even in the early 90s on Intel chips, in order to simplify the design process, and help explain the basic concepts. If I like what I’ve done, when the time comes, maybe I’ll add more realistic features, such as multiple pipelines (superscalar) and out-of-order execution, or I’ll design support for more esoteric features (like barrel processing), to see how readily (if at all) they are implemented and to provide some context about where microprocessors can go from the basic 5-stage pipeline.

The real goal here is educational in nature. Microprocessors are incredibly complicated devices, and so most online descriptions are terse at best. Despite that, I think people should be able to learn, for free, exactly how a microprocessor works. However, I can’t explain how an x86 chip works, for a number of reasons. First, I don’t actually know. I have a pretty good understanding of the elements from which it is built, but I’ve spent almost no time studying the ISA or reading papers on how Intel has actually implemented things. Second, I’d hate to speculate and be totally wrong, and then have people read it and think that was how it works. In contrast, I do understand the principles upon which RISC microprocessors (like MIPS and ARM) are based, so I can readily make up an instruction set that it is similar to MIPS, implement it, and then talk at great length about how it works. Hopefully, then, a younger version of me can find this online, look through it, and then be able to answer all those questions I had until college about how computers actually do things. If software and programming can be well documented and available for free to learn from, then hardware should be too.

If you would like to contribute descriptions, Verilog, or simulation code (which will mostly be written in C), please let me know by posting in the comments.

Coming soon: The Master Plan. I’ll lay out precisely what the objectives are and give an overview of how the project will progress as a whole.

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Authoritative Opinion » The Microprocessor Project

TMP: Master Plan

The Microprocessor Project: Overview